The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventor, to the extent that it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Multi-port memories, such as dual-port static random access memories (SRAM) and dual-port dynamic random access memories (DRAM), are configured to receive multiple instructions on the same clock cycle. This enables the multi-port memory to, for example, concurrently write and read data. This includes concurrently reading data from, and writing to, the same DRAM array. However, if the read and write addresses associated with the concurrently received read and write commands are the same address, then the read data that is output from the memory device cannot be guaranteed. This is because a data word line is in an unknown state during a write operation, and any data concurrently read from it is therefore unreliable. To address this problem in conventional systems, a memory controller or other device that arbitrates access to a multi-port memory avoids issuing concurrent read and write commands to the memory device when the addresses are the same.